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| FUJITSU SEMICONDUCTOR DATA SHEET DS07-16804-1E 32-bit Proprietary Microcontroller CMOS FR60Lite MB91210 Series MB91F211/213/F213/V210 DESCRIPTIONS MB91210 series is Fujitsu's general-purpose 32-bit RISC microcontroller, which is designed for embedded control applications that require high-speed real-time processing of consumer appliances. This microcontroller uses FR60Lite as its CPU, compatible with other products in the FR* family. This series incorporates a built-in LIN-UART and CAN controller. * : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited. FEATURES * FR CPU * 32-bit RISC, load/store architecture, 5-stage pipeline * Maximum operating frequency : 40 MHz (Source oscillation is 4 MHz - PLL clock multiplier system) * 16-bit fixed length instructions (basic instructions), one instruction per cycle * Memory-memory transfer instructions, bit processing instructions, barrel shift instructions - Instructions adapted for embedded applications * Function entry/exit instructions, multiple-register load/store instructions - Instructions supporting high-level language * Register interlock function - Easier assembler coding enabled (Continued) Be sure to refer to the "Check Sheet" for the latest cautions on development. "Check Sheet" is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html "Check Sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development. Copyright(c)2007 FUJITSU LIMITED All rights reserved MB91210 Series (Continued) * Built-in multiplier supported at the instruction level - Signed 32-bit multiplication: 5 cycles - Signed 16-bit multiplication: 3 cycles * Interrupt (PC/PS save) : 6 cycles, 16 priority levels * Harvard architecture allowing program access and data access to be executed simultaneously. * Instruction compatible with the FR family * Internal ROM size & ROM type * MASK ROM : 544 Kbytes (MB91213) * Flash Memory : 288 Kbytes (MB91F211) : 544 Kbytes (MB91F213) * Internal RAM size : 24 Kbytes (MB91213/F213) : 16 Kbytes (MB91F211) * DMA Controller * Capable of simultaneous operation of up to 5 channels * Two transfer sources (internal peripheral/software) * Bit Search Module (for REALOS) * Search for the position of the first bit that changes from "1" to "0" in one word, from the MSB * LIN-UART (7 channels) * Asynchronous clock communication (start-stop synchronization), synchronous clock communication * Synch-Break detection * Dedicated built-in baud-rate generator for each channel * SPI compliant (Mode 2 : clock synchronous communication mode) * CAN Controller (3 channels) * Maximum transfer rate : 1 Mbps * 32 message buffer * Timers * 16-bit reload timer (3 channels) Selectable internal clock from 2/8/32 divisions * 16-bit free-run timer (4 channels) * Output compare (8 channels) * Input capture (8 channels) * 8/16-bit PPG (16 channels/8 channels) Selectable clock source from 1/2/16/64 division of peripheral clock * Interrupt Controller * Interrupts from internal peripherals * Priority level can be set by software (16 levels) * External Interrupt (16 channels) * Selectable input from several pins * Can be used as CAN WAKEUP Noise filter is inserted to CAN WAKEUP (Typ = 4 s) * A/D Converter (32 channels) * 10-bit resolution * Sequential comparison Conversion time : 3 s * Conversion modes (single conversion mode and scan conversion mode) * Activation trigger (software/external trigger/peripheral interrupt) 2 MB91210 Series * Other Interval Timer/Counter * 16-bit timebase timer/watchdog timer * Other Features * Has a built-in oscillation circuit as a clock source, and also can select PLL multiplier * INITX is provided as a reset pin * Additionally, a watchdog timer reset and software resets are provided * Stop mode, sleep mode and real time clock mode supported as low-power consumption modes. Low-power operation using 32 kHz CPU operation enabled * Gear function Clock can be generated from various combinations of PLL multiplier setting (1/2/4/8/10) and division setting (1 to 16) for each clock * Built-in timebase timer * Package : LQFP-100, LQFP-144 * CMOS technology (0.18 m) * Power supply voltage : 3.5 V to 5.5 V 1.8 V is supplied to internal circuit from step-down circuit * Comparison of Functions MB91V210 Evaluation product Package ROM/Flash size RAM size External interrupt DMA Controller External sub-clock Suspected sub-clock RTC CAN Controller BGA-420 External SRAM 4 Kbytes + 32 Kbytes 16 channels 5 channels Correspondence Non-correspondence Yes 3 channels (128 msg/ch) MB91F211 Flash memory product LQFP-100 288 Kbytes 4 Kbytes + 12 Kbytes 16 channels 5 channels Correspondence Correspondence Yes 1 channel (32 msg/ch) 4 channels (LIN corresponding) 1 channel (LIN non-corresponding) 3 channels 2 channels 4 channels 4 channels 8bits x 8 channels (16bits x 4 channels) 16 channels MB91F213 Flash memory product MB91213 MASK ROM product LQFP-144 544 Kbytes 4 Kbytes + 20 Kbytes 16 channels 5 channels Correspondence Non-correspondence Yes 3 channels (32 msg/ch) LIN-UART 7 channels 7 channels Reload Timer Free-run timer ICU OCU 8/16bits PPG A/D Converter 3 channels 4 channels 8 channels 8 channels 8bits x 16 channels (16bits x 8 channels) 32 channels 3 channels 4 channels 8 channels 8 channels 8bits x 16 channels (16bits x 8 channels) 32 channels 3 4 *MB91F211 PIN ASSIGNMENT MB91210 Series P45/IN1 P46/IN2 P47/IN3 P50/PPG1 P51/PPG3 P52/PPG5 P53/PPG7 P54 P55 P56 P57 P60 PE0/SIN2 PE1/SOT2 PE2/SCK2 P70/RX0/INT8 P71/TX0 P74/OCU0 P75/OCU1 P76/OCU2 P77/OCU3 P80/FRCK0 P81/FRCK1 C VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 FRT OCU CAN UART PPG ICU RLT UART (PPG) UART RLT ADC (TOP VIEW) (FPT-100P-M20) INT RLT UART UART INT VCC P82 P83 P84/TIN2 P85/TOT2 P90/AN0/PPG0R P91/AN1/PPG2R P92/AN2/PPG4R P93/AN3/PPG6R P94/AN4 P95/AN5 P96/AN6 P97/AN7 AVCC AVSS/AVRL AVRH PA0/AN8 PA1/AN9 PA2/AN10 PA3/AN11 PA4/AN12 PA5/AN13 PA6/AN14 PA7/AN15 PB0/INT0R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS X1 X0 MD3 MD2 MD1 MD0 INITX PD7/SCK1 PD6/SOT1 PD5/SIN1 PD4/SCK0 PD3/SOT0 PD2/SIN0 PD1/TOT0 PD0/TIN0/ATGX VCC VSS PB7/INT7R PB6/INT6R PB5/INT5R PB4/INT4R PB3/INT3R PB2/INT2R PB1/INT1R 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P44/IN0 P43 P42 P41 P40 P17/SCK4 P16/SOT4 P15/SIN4 VCC VSS P14/SCK3 P13/SOT3 P12/SIN3 P11/TOT1 P10/TIN1 P07/INT15R P06/INT14R P05/INT13R P04/INT12R P03/INT11R P02/INT10R P01/INT9R P00/INT8R X1A (P73) X0A (P72) *MB91213/F213 VCC P37/INT15 P40/PPG9 P41/PPGB P42/PPGD P43/PPGF P44/IN0 P45/IN1 P46/IN2 P47/IN3 P50/PPG1 P51/PPG3 P52/PPG5 P53/PPG7 P54/IN4 P55/IN5 P56/IN6 P57/IN7 P60/OUT6 P61/OUT7 P62 P63 VSS VCC P64 P70/RX0/INT8 P71/TX0 P72/RX1/INT9 P73/TX1 P74/OCU0 P75/OCU1 P76/OCU2 P77/OCU3 P80/FRCK0 C VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 OCU OCU FRT CAN INT ICU PPG ICU PPG FRT RLT (PPG) PPG (UART) (TOP VIEW) ADC (FPT-144P-M08) (INT) UART UART RLT OCU UART UART (INT) VCC P81/FRCK1 P82/FRCK2 P83/FRCK3 P84/TIN2 P85/TOT2 P90/AN0/PPG0R P91/AN1/PPG2R P92/AN2/PPG4R P93/AN3/PPG6R P94/AN4/PPG8R P95/AN5/PPGAR P96/AN6/PPGCR P97/AN7/PPGER PA0/AN8/SIN2R PA1/AN9/SOT2R PA2/AN10/SCK2R PA3/AN11 PA4/AN12 PA5/AN13 PA6/AN14 PA7/AN15 AVCC AVSS/AVRL AVRH PB0/AN16/INT0R PB1/AN17/INT1R PB2/AN18/INT2R PB3/AN19/INT3R PB4/AN20/INT4R PB5/AN21/INT5R PB6/AN22/ITN6R PB7/AN23/INT7R PC0/AN24 PC1/AN25 VSS ADC RLT UART UARTUART INT 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VSS X1 X0 MD3 MD2 MD1 MD0 INITX PF7/INT7 PF6/INT6 PF5/INT5 PF4/INT4 PF3/INT3 PF2/INT2 PF1/INT1 VCC VSS PF0/INT0 PE2/SCK2 PE1/SOT2 PE0/SIN2 PD7/SCK1 PD6/SOT1 PD5/SIN1 PD4/SCK0 PD3/SOT0 PD2/SIN0 PD1/TOT0 PD0/TIN0/ATGX PC7/AN31 PC6/AN30 PC5/AN29 PC4/AN28 PC3/AN27 PC2/AN26 VCC 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VSS P36/INT14 P35/INT13 P34/INT12 P33/INT11 P32/INT10 P31/TX2 P30/RX2/INT10C P27/PPGE P26/PPGC P25/PPGA P24/PPG8 P23/PPG6 P22/PPG4 P21/PPG2 P20/PPG0 P17/SCK4 P16/SOT4 P15/SIN4 P14/SCK3 P13/SOT3 P12/SIN3 P11/TOT1 P10/TIN1 P07/OUT5/INT15R P06/OUT4/INT14R P05/SCK6/INT13R P04/SOT6/INT12R P03/SIN6/INT11R P02/SCK5/INT10R P01/SOT5/INT9R P00/SIN5/INT8R VCC VSS X1A X0A MB91210 Series 5 MB91210 Series PIN DESCRIPTIONS * Pin Functions Pin no. LQFP* 68 72 71 to 69 76 77 78 1 LQFP* 106 107 101 105 109 110 113 2 Pin name X0 X1 INITX MD3 X0A X1A P00 Function name X0 X1 INITX MD3 MD2 to MD0 X0A X1A P00 SIN5 INT8R P01 I/O circuit type*3 OA OB D E C WA WB Function Oscillator input pin Oscillator output pin System reset input pin Operation mode input pin Operation mode input pins Sub-oscillation input pin Sub-oscillation output pin General purpose I/O port UART5 data input External interrupt 8 input (select with P70) General purpose I/O port 104 to 102 MD2 to MD0 A 79 114 P01 SOT5 INT9R P02 A UART5 data output External interrupt 9 input (select with P71) General purpose I/O port 80 115 P02 SCK5 INT10R P03 A UART5 clock I/O External interrupt 10 input (select with P32) General purpose I/O port 81 116 P03 SIN6 INT11R P04 A UART6 data input External interrupt 11 input (select with P33) General purpose I/O port 82 117 P04 SOT6 INT12R P05 A UART6 data output External interrupt 12 input (select with P34) General purpose I/O port 83 118 P05 SCK6 INT13R P06 A UART6 clock I/O External interrupt 13 input (select with P35) General purpose I/O port 84 119 P06 OUT4 INT14R P07 A OCU4 output External interrupt 14 input (select with P36) General purpose I/O port 85 120 P07 OUT5 INT15R P10 TIN1 A OCU5 output External interrupt 15 input (select with P37) General purpose I/O port External event input of reload timer 1 (Continued) 86 121 P10 A 6 MB91210 Series Pin no. LQFP*1 87 88 89 90 93 94 95 LQFP*2 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 Pin name P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 Function name P11 TOT1 P12 SIN3 P13 SOT3 P14 SCK3 P15 SIN4 P16 SOT4 P17 SCK4 P20 PPG0 P21 PPG2 P22 PPG4 P23 PPG6 P24 PPG8 P25 PPGA P26 PPGC P27 PPGE P30 RX2 INT10C P31 TX2 I/O circuit type*3 A A A A A A A A A A A A A A A Function General purpose I/O port Reload timer 1 output General purpose I/O port UART3 data input General purpose I/O port UART3 data output General purpose I/O port UART3 clock I/O General purpose I/O port UART4 data input General purpose I/O port UART4 data output General purpose I/O port UART4 clock I/O General purpose I/O port PPG0 output General purpose I/O port PPG2 output General purpose I/O port PPG4 output General purpose I/O port PPG6 output General purpose I/O port PPG8 output General purpose I/O port PPGA output General purpose I/O port PPGC output General purpose I/O port PPGE output General purpose I/O port CAN2 input External interrupt 10 input (select with P32) General purpose I/O port CAN2 output (Continued) 7 137 P30 A 138 P31 A MB91210 Series Pin no. LQFP*1 96 97 98 99 100 1 2 3 4 5 6 LQFP*2 139 140 141 142 143 2 3 4 5 6 7 8 9 10 11 12 13 Pin name P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52 Function name P32 INT10 P33 INT11 P34 INT12 P35 INT13 P36 INT14 P37 INT15 P40 PPG9 P41 PPGB P42 PPGD P43 PPGF P44 IN0 P45 IN1 P46 IN2 P47 IN3 P50 PPG1 P51 PPG3 P52 PPG5 I/O circuit type*3 A A A A A A A A A A A A A A A A A Function General purpose I/O port External interrupt 10 input (select with P30) General purpose I/O port External interrupt 11 input General purpose I/O port External interrupt 12 input General purpose I/O port External interrupt 13 input General purpose I/O port External interrupt 14 input General purpose I/O port External interrupt 15 input General purpose I/O port PPG9 output General purpose I/O port PPGB output General purpose I/O port PPGD output General purpose I/O port PPGF output General purpose I/O port ICU0 input General purpose I/O port ICU1 input General purpose I/O port ICU2 input General purpose I/O port ICU3 input General purpose I/O port PPG1 output General purpose I/O port PPG3 output General purpose I/O port PPG5 output (Continued) 8 MB91210 Series Pin no. LQFP*1 7 8 9 10 11 12 16 LQFP*2 14 15 16 17 18 19 20 21 22 25 26 Pin name P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P70 Function name P53 PPG7 P54 IN4 P55 IN5 P56 IN6 P57 IN7 P60 OUT6 P61 OUT7 P62 P63 P64 P70 RX0 INT8 P71 TX0 P72 RX1 INT9 P73 TX1 P74 OCU0 P75 OCU1 P76 OCU2 P77 OCU3 I/O circuit type*3 A A A A A A A A A A A Function General purpose I/O port PPG7 output General purpose I/O port ICU4 input General purpose I/O port ICU5 input General purpose I/O port ICU6 input General purpose I/O port ICU7 input General purpose I/O port OCU6 output General purpose I/O port OCU7 output General purpose I/O port General purpose I/O port General purpose I/O port General purpose I/O port CAN0 input External interrupt 8 input (select with P00) General purpose I/O port CAN0 output General purpose I/O port CAN1 input External interrupt 9 input (select with P01) General purpose I/O port CAN1 output General purpose I/O port OCU0 output General purpose I/O port OCU1 output General purpose I/O port OCU2 output General purpose I/O port OCU3 output (Continued) 9 17 27 P71 A (76) * 4 28 P72 A (77) *4 18 19 20 21 29 30 31 32 33 P73 P74 P75 P76 P77 A A A A A MB91210 Series Pin no. LQFP*1 22 23 27 28 29 30 LQFP*2 34 38 39 40 41 42 Pin name P80 P81 P82 P83 P84 P85 Function name P80 FRCK0 P81 FRCK1 P82 FRCK2 P83 FRCK3 P84 TIN2 P85 TOT2 P90 AN0 PPG0R P91 I/O circuit type*3 A A A A A A Function General purpose I/O port External clock input of free-run timer 0 General purpose I/O port External clock input of free-run timer 1 General purpose I/O port External clock input of free-run timer 2 General purpose I/O port External clock input of free-run timer 3 General purpose I/O port External event input of reload timer 2 General purpose I/O port Reload timer 2 output General purpose I/O port A/D converter analog input PPG0 output (select with P20) General purpose I/O port 31 43 P90 B 32 44 P91 AN1 PPG2R P92 B A/D converter analog input PPG2 output (select with P21) General purpose I/O port 33 45 P92 AN2 PPG4R P93 B A/D converter analog input PPG4 output (select with P22) General purpose I/O port 34 46 P93 AN3 PPG6R P94 B A/D converter analog input PPG6 output (select with P23) General purpose I/O port 35 47 P94 AN4 PPG8R P95 B A/D converter analog input PPG8 output (select with P24) General purpose I/O port 36 48 P95 AN5 PPGAR P96 B A/D converter analog input PPGA output (select with P25) General purpose I/O port 37 49 P96 AN6 PPGCR B A/D converter analog input PPGC output (select with P26) (Continued) 10 MB91210 Series Pin no. LQFP*1 38 LQFP*2 50 Pin name Function name P97 I/O circuit type*3 Function General purpose I/O port P97 AN7 PPGER PA0 B A/D converter analog input PPGE output (select with P27) General purpose I/O port 42 51 PA0 AN8 SIN2R PA1 B A/D converter analog input UART2 data input (select with PE0) General purpose I/O port 43 52 PA1 AN9 SOT2R PA2 B A/D converter analog input UART2 data output (select with PE1) General purpose I/O port 44 53 PA2 AN10 SCK2R PA3 AN11 PA4 AN12 PA5 AN13 PA6 AN14 PA7 AN15 PB0 AN16 INT0R PB1 B A/D converter analog input UART2 clock I/O (select with PE2) General purpose I/O port A/D converter analog input General purpose I/O port A/D converter analog input General purpose I/O port A/D converter analog input General purpose I/O port A/D converter analog input General purpose I/O port A/D converter analog input General purpose I/O port A/D converter analog input External interrupt 0 input (select with PF0) General purpose I/O port 45 46 47 48 49 54 55 56 57 58 PA3 PA4 PA5 PA6 PA7 B B B B B 50 62 PB0 B 51 63 PB1 AN17 INT1R PB2 B A/D converter analog input External interrupt 1 input (select with PF1) General purpose I/O port 52 64 PB2 AN18 INT2R PB3 B A/D converter analog input External interrupt 2 input (select with PF2) General purpose I/O port 53 65 PB3 AN19 INT3R B A/D converter analog input External interrupt 3 input (select with PF3) (Continued) 11 MB91210 Series Pin no. LQFP*1 54 LQFP*2 66 Pin name Function name PB4 I/O circuit type*3 Function General purpose I/O port PB4 AN20 INT4R PB5 B A/D converter analog input External interrupt 4 input (select with PF4) General purpose I/O port 55 67 PB5 AN21 INT5R PB6 B A/D converter analog input External interrupt 5 input (select with PF5) General purpose I/O port 56 68 PB6 AN22 INT6R PB7 B A/D converter analog input External interrupt 6 input (select with PF6) General purpose I/O port 57 69 PB7 AN23 INT7R PC0 AN24 PC1 AN25 PC2 AN26 PC3 AN27 PC4 AN28 PC5 AN29 PC6 AN30 PC7 AN31 PD0 TIN0 ATGX PD1 TOT0 PD2 SIN0 B A/D converter analog input External interrupt 7 input (select with PF7) General purpose I/O port A/D converter analog input General purpose I/O port A/D converter analog input General purpose I/O port A/D converter analog input General purpose I/O port A/D converter analog input General purpose I/O port A/D converter analog input General purpose I/O port A/D converter analog input General purpose I/O port A/D converter analog input General purpose I/O port A/D converter analog input General purpose I/O port External event input of reload timer 0 A/D converter external trigger input General purpose I/O port Reload timer 0 output General purpose I/O port UART0 data input (Continued) 70 71 74 75 76 77 78 79 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 B B B B B B B B 60 80 PD0 A 61 62 81 82 PD1 PD2 A A 12 MB91210 Series Pin no. LQFP*1 63 64 65 66 67 13 14 15 26, 59, 92 LQFP*2 83 84 85 86 87 88 89 90 91 94 95 96 97 98 99 100 1, 24, 37, 73, 93, 112 Pin name PD3 PD4 PD5 PD6 PD7 PE0 PE1 PE2 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 VCC Function name PD3 SOT0 PD4 SCK0 PD5 SIN1 PD6 SOT1 PD7 SCK1 PE0 SIN2 PE1 SOT2 PE2 SCK2 PF0 INT0 PF1 INT1 PF2 INT2 PF3 INT3 PF4 INT4 PF5 INT5 PF6 INT6 PF7 INT7 -- I/O circuit type*3 A A A A A A A A A A A A A A A A -- Function General purpose I/O port UART0 data output General purpose I/O port UART0 clock I/O General purpose I/O port UART1 data input General purpose I/O port UART1 data output General purpose I/O port UART1 clock I/O General purpose I/O port UART2 data input General purpose I/O port UART2 data output General purpose I/O port UART2 clock I/O General purpose I/O port External interrupt 0 input General purpose I/O port External interrupt 1 input General purpose I/O port External interrupt 2 input General purpose I/O port External interrupt 3 input General purpose I/O port External interrupt 4 input General purpose I/O port External interrupt 5 input General purpose I/O port External interrupt 6 input General purpose I/O port External interrupt 7 input Power supply pins (5 V) (Continued) 13 MB91210 Series (Continued) Pin no. LQFP*1 25, 58, 75, 91 24 39 40 41 LQFP*2 23, 36, 72, 92, 108, 111, 144 35 59 60 61 Pin name Function name -- -- -- -- -- -- I/O circuit type*3 -- -- -- -- -- -- Function VSS C AVCC AVSS AVRL AVRH Power supply pins (0 V) Power stabilization capacitance pin Analog power supply pin Analog power supply pin Base power supply pin for A/D converter Base power supply pin for A/D converter *1 : FPT-100P-M20 *2 : FPT-144P-M08 *3 : For information about the I/O circuit type, refer to " I/O CIRCUIT TYPE". *4 : MB91F211 can be selected by MD3 to MD0 of mode pins. MD pin 0000 0011 Other than above 76 pin X0A P72 Setting prohibited 77 pin X1A P73 P72 and P73 function as general-purpose I/O ports only. 14 MB91210 Series I/O CIRCUIT TYPE Group Circuit Type Pull-up control Remarks * CMOS level output * CMOS hysteresis input (with standby-time input shutdown function) * Automotive input (with standby-time input shutdown function) P-ch P-ch Pout Nout N-ch N-ch A Pull-down control CMOS Hysteresis input Automotive input Standby control for input control Pull-up control * CMOS level output * CMOS hysteresis input (with standby-time input shutdown function) * Automotive input (with standby-time input shutdown function) * A/D analog input P-ch P-ch Pout Nout N-ch N-ch B Pull-down control CMOS Hysteresis input Automotive input Standby control for input control Analog input (Continued) 15 MB91210 Series (Continued) Group MASK ROM product CMOS Hysteresis input Flash memory product N-ch Circuit Type Remarks Mask ROM product * CMOS hysteresis input * MD 2 : Pull-down provided Flash memory product * High-voltage control signal for test provided * MD 2 : No pull-down provided C N-ch N-ch N-ch Control signal Mode input N-ch Diffused resistor CMOS hysteresis input D Pull-up resistor CMOS Hysteresis input CMOS hysteresis input CMOS Hysteresis input E Pull-down resistor X1 Xout Oscillation circuit High speed oscillation feedback resistance : approx. 1 M OA OB X0 Standby control signal Oscillation circuit Low speed oscillation feedback resistance : approx. 20 M X1A Xout WA WB X0A Standby control signal 16 MB91210 Series HANDLING DEVICES * Preventing latch-up Latch-up may occur in a CMOS IC, if a voltage greater than VCC pin or less than VSS pin is applied to input and output pin, or if an above-rating voltage is applied between VCC and VSS. When latch-up occurs, it may significantly increase the power supply current, and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. * Treatment of unused pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by performing a pull-up or pull-down with a resistance of 2 k or more. An unused I/O pin should be set to the output status and left open. When set to the input status, it should be handled in the same way as an input pin. * About power supply pins If there are multiple VCC and VSS pins, from the point of view of device design pins to be of the same potential are connected inside the device to prevent such malfunctioning as latch-up. However, you must connect all the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. Furthermore, it is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC and VSS near this device. This device incorporates a regulator. When using the device with 5 V power supply, apply that power supply to the VCC pin and always connect a 1 F or greater capacitor to the C pin for the regulator. * Crystal oscillator circuit Noise near the X0/X1 pins and X0A/X1A pins may cause the device to malfunction. Design the PC board such that X0/X1 pins, X0A/X1A pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to the ground are placed as near one another as possible. When routing the X0 and X1 signals, they should be shielded for use on the board. Caution must be taken especially when using a pin next to the X0. It is strongly recommended to design the PC board artwork with the X0, X1, X0A and X1A pins surrounded by ground plane because stable operation can be expected with such a layout. In addition, a sub clock is required even when a dual clock product is used as a single clock product. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device. * Notes on using external clock When an external clock is used, supply the opposite phase clock to X0/X1 pins, simultaneously. Note that input only to X0 pin cannot be used. Also, when an external clock is used, do not use the STOP mode (oscillation stop mode). (This is because the X1 pin stops at "H" output in the STOP mode.) Example Application of External Clock (Normal) X0 X1 MB91210 series Note : STOP mode (oscillation stop mode) cannot be used. 17 MB91210 Series * Handling of NC/OPEN pins Always leave NC pins and OPEN pins open. * Mode pins (MD0 to MD3) These pins should be connected directly to VCC or VSS pins. To prevent the device erroneously switching to test mode due to noise, design the PC board such that the distance between the mode pins and VCC or VSS pins is as short as possible and the connection impedance is now. * Power-on Upon power-on, INITX pin must have been set to "L" level. * Source oscillation input upon power-on Upon power-on, never fail to input the clock until the oscillation stabilization wait is cancelled. * About Flash write Note that Flash write/erase is not possible in the sub mode. * Treatment of power supply pins on A/D converter Connect to ensure "AVCC = AVRH = VCC and AVSS = VSS" even if the A/D converter is not in use. * Power-on sequence for power supply analog input of A/D converter Always supply power to the A/D converter (AVCC and AVRH) and apply analog input (AN0 to AN 31) after turning on the digital power supply (VCC). Also, turn off the power supply for the A/D converter and analog input before turning off the digital power supply (VCC). In so doing, the power supply must be turn on and off so that AVRH does not exceed AVCC. Even when using a pin shared with analog input as an input port, ensure that the input voltage does not exceed AVCC (There is no problem in turning on or off the A/D converter (AVCC and AVRH) and digital power supplies at the same time). * Caution on operations during PLL clock mode Even if the oscillator comes off or the clock input stops with the PLL clock selected for this microcontroller, the microcontroller may continue to operate at the free-running frequency of the PLL's internal self-oscillating oscillator circuit. Performance of this operation is not guaranteed. 18 MB91210 Series BLOCK DIAGRAM FR60Lite CPU core Bit search D-bus RAM Flash F-bus RAM RX0 to RX2 TX0 to TX2 Bus converter DMA controller CAN 32 16 adapter X0, X1 X0A, X1A MD3 to MD0 INITX Clock control PORT I/F PORT Interrupt controller INT0 to INT15 (INT0R to INT15R) INT10C SIN0 to SIN6 (SIN2R) SOT0 to SOT6 (SOT2R) SCK0 to SCK6 (SCK2R) Reload timer External interrupt TIN0 to TIN2 TOT0 to TOT2 IN0 to IN7 Input capture LIN-UART Free-run timer BRG for UART Output compare Real-time clock FRCK0 to FRCK3 OUT0 to OUT7 8/16 bits PPG AN0 to AN31 ATGX 10 bits A/D converter PPG0 to PPGF (PPG0R, 2R, 4R, PPG6R, 8R, AR, PPGCR, ER) 19 MB91210 Series MEMORY SPACE * Memory map MB91V210 I/O 0000 0400H 0000 0000H MB91F211 I/O I/O Access prohibit CAN Access prohibit F- bus RAM D- bus RAM MB91F213 I/O I/O Access prohibit CAN Access prohibit F- bus RAM D- bus RAM Direct addressing area I/O 0001 0000H 0002 0000H 0002 0100H 0002 0300H 0003 8000H 0003 B000H 0003 D000H 0004 0000H 0004 1000H 0005 0000H Access prohibit CAN Access prohibit F- bus RAM D- bus RAM Access prohibit Access prohibit Access prohibit 0007 8000H External SRAM 000B 8000H 0010 0000H Access prohibit Access prohibit Access prohibit 20 MB91210 Series MODE SETTINGS In the FR family, the operating mode is set by the mode pins (MD3, 2, 1, 0) and the mode register (MODR). * Mode pins There are four mode pins (MD3 to MD0) to specify how to fetch the mode vector. Settings other than these in the table are prohibited. Mode pin MD3 MD2 MD1 MD0 0 0 0 0 0 0 0 1 Mode name Internal ROM mode vector External ROM mode vector Reset vector access area Internal External Setting is prohibited in this device. Remarks Note: In the FR family, the external mode vector fetch by a multiplex bus is not supported. * Mode data Data written to the mode register by a mode vector fetch is called mode data. After an operating mode has been set in the mode register (MODR), the device operates in that operating mode. The mode data is set by all reset sources. User programs cannot set data to the mode register. Detailed description of mode data bit31 bit30 bit29 bit28 bit27 bit26 bit25 bit24 0 0 0 0 0 ROM WTH WTH Operation mode setting bits [bit7 to bit3] Reserved bits Always set the value to "00000B". Normal operation is not guaranteed when a value other than "00000B" is set. [bit2] ROMA (Internal ROM enable bit) This bit sets whether to enable F-bus ROM areas. ROMA 0 1 Function External ROM mode Internal ROM mode F-bus ROM is enabled. Remarks Internal ROM area (50000H to FFFFFH) becomes the external area. 21 MB91210 Series [bit1, bit0] WTH1, WTH0 (Bus width specification bits) These bits set the bus width specification in external bus mode. In external bus mode, this value is set in the DBW0 bit of ACR0 (CS0 area). WTH1 WTH0 Function 0 0 1 1 0 1 0 1 8-bit bus width 16-bit bus width -- Single-chip mode Remarks Setup prohibited Setup prohibited Setup prohibited Single-chip mode 22 MB91210 Series I/O MAP [How to read the map] Address 000000H Register +0 PDR0 [R/W] B XXXXXXXX +1 PDR1 [R/W] B XXXXXXXX +2 PDR2 [R/W] B XXXXXXXX +3 PDR3 [R/W] B XXXXXXXX Block T-unit Port data register Read/Write attribute, Access unit (B : byte, H : halfword, W : word) Initial value after reset Register name (First-column register at address 4n; second-column register at 4n + 1, etc.) Location of left-most register (When using word access, the register in column 1 is in the MSB side of the data.) Notes: Initial values of register bits are represented as follows : * "1" : Initial value "1" * "0" : Initial value "0" * "X" : Initial value "undefined" * "-" : No physical register present at this location. Access by any undescribed data is prohibited. 23 MB91210 Series Address 000000H 000004H 000008H 00000CH 000010H to 00003CH 000040H Register +0 +1 +2 +3 Block PDR0(R/W) B, H XXXXXXXX PDR4(R/W) B, H XXXXXXXX PDR8(R/W) B, H --XXXXXX PDRC(R/W) B, H XXXXXXXX PDR1(R/W) B, H XXXXXXXX PDR5(R/W) B, H XXXXXXXX PDR9(R/W) B, H XXXXXXXX PDRD(R/W) B, H XXXXXXXX -- PDR2(R/W) B, H XXXXXXXX PDR6(R/W) B, H XXXXXXXX PDRA(R/W) B, H XXXXXXXX PDRE(R/W) B, H -----XXX PDR3(R/W) B, H XXXXXXXX PDR7(R/W) B, H XXXXXXXX PDRB(R/W) B, H XXXXXXXX PDRF(R/W) B, H XXXXXXXX Reserved Port Data Register EIRR0(R/W) B, H, W 00000000 DICR(R/W) B, H, W -------0 ENIR0(R/W) B, H, W 00000000 HRCL(R/W BIT4 only R) B 0--11111 ELVR0(R/W) B, H, W 00000000 00000000 External Interrupt (INT0 to INT7) Delay Interrupt Module 000044H -- TMR0(R) H, W XXXXXXXX XXXXXXXX TMCSR0(R/W, only bit6: R) B, H, W ----0000 00000000 TMR1(R) H, W XXXXXXXX XXXXXXXX TMCSR1(R/W, only bit6: R) B, H, W ----0000 00000000 TMR2(R) H, W XXXXXXXX XXXXXXXX TMCSR2(R/W, only bit6: R) B, H, W ----0000 00000000 SSR0 (bit10 to 8: R/W, bit15 to 11: R) B, H, W 00001000 BGR10(R/W) B, H, W 10000000 RDR0/TDR0(R/W, only bit3, 2: W) B, H, W 00000000 BGR00(R/W) B, H, W 00000000 000048H 00004CH 000050H 000054H 000058H 00005CH TMRLR0(W) H, W XXXXXXXX XXXXXXXX -- TMRLR1(W) H, W XXXXXXXX XXXXXXXX -- TMRLR2(W) H, W XXXXXXXX XXXXXXXX -- SCR0(R/W, only 10bit: W) B, H, W 00000000 ESCR0 (R/W) B, H, W 00000100 SMR0(R/W, only bit3, 2: W) B, H, W 00000000 ECCR0(bit6:W bit5-3:R/W bit10:R) B, H, W 000000XX Reload Timer 0 Reload Timer 1 Reload Timer 2 000060H UART 0 000064H (Continued) 24 MB91210 Series Address Register +0 +1 +2 +3 Block 000068H SCR5(R/W, only 10bit: W) B, H, W 00000000 ESCR5 (R/W) B, H, W 00000100 SCR6(R/W, only 10bit: W) B, H, W 00000000 ESCR6 (R/W) B, H, W 00000100 SMR5(R/W, only bit3, 2: W) B, H, W 00000000 ECCR5(bit6:W bit5-3:R/W bit10:R) B, H, W 000000XX SMR6(R/W, only bit3, 2: W) B, H, W 00000000 ECCR6(bit6:W bit5-3:R/W bit10:R) B, H, W 000000XX -- SSR5 (bit10 to 8: R/W, bit15 to 11: R) B, H, W 00001000 BGR15(R/W) B, H, W 10000000 SSR6 (bit10 to 8: R/W, bit15 to 11: R) B, H, W 00001000 BGR16(R/W) B, H, W 10000000 RDR5/TDR5(R/W, only bit3, 2: W) B, H, W 00000000 BGR05(R/W) B, H, W 00000000 RDR6/TDR6(R/W, bit3, 2: W) B, H, W 00000000 UART 5 00006CH 000070H UART 6 BGR06(R/W) B, H, W 00000000 000074H 000078H to 0000ACH SCR1(R/W, only 10bit: W) B, H, W 00000000 ESCR1 (R/W) B, H, W 00000100 SCR2(R/W, only 10bit: W) B, H, W 00000000 ESCR2 (R/W) B, H, W 00000100 SCR3(R/W, only 10bit: W) B, H, W 00000000 ESCR3 (R/W) B, H, W 00000100 Reserved SSR1 (bit10 to 8: R/W, bit15 to 11: R) B, H, W 00001000 BGR11(R/W) B, H, W 10000000 SSR2 (bit10 to 8: R/W, bit15 to 11: R) B, H, W 00001000 BGR12(R/W) B, H, W 10000000 SSR3 (bit10 to 8: R/W, bit15 to 11: R) B, H, W 00001000 BGR13(R/W) B, H, W 10000000 0000B0H SMR1(R/W, only bit3, 2: W) B, H, W 00000000 ECCR1(bit6:W bit5-3:R/W bit10:R) B, H, W 000000XX SMR2(R/W, only bit3, 2: W) B, H, W 00000000 ECCR2(bit6:W bit5-3:R/W bit10:R) B, H, W 000000XX SMR3(R/W, only bit3, 2: W) B, H, W 00000000 ECCR3(bit6:W bit5-3:R/W bit10:R) B, H, W 000000XX RDR1/TDR1(R/W, bit3, 2: W) B, H, W 00000000 UART 1 BGR01(R/W) B, H, W 00000000 RDR2/TDR2(R/W, bit3, 2: W) B, H, W 00000000 UART 2 BGR02(R/W) B, H, W 00000000 RDR3/TDR3(R/W, bit3, 2: W) B, H, W 00000000 UART 3 BGR03(R/W) B, H, W 00000000 (Continued) 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 25 MB91210 Series Address Register +0 +1 +2 +3 Block 0000C8H SCR4(R/W, only 10bit: W) B, H, W 00000000 ESCR4 (R/W) B, H, W 00000100 SMR4(R/W, only bit3, 2: W) B, H, W 00000000 ECCR4(bit6:W bit53:R/W bit1-0:R) B, H, W 000000XX SSR4 (bit10 to 8: R/W, bit15 to 11: R) B, H, W 00001000 BGR14(R/W) B, H, W 10000000 RDR4/TDR4(R/W, bit3, 2: W) B, H, W 00000000 UART 4 BGR04(R/W) B, H, W 00000000 External interrupt (INT8 to INT15) Free Run Timer 0 Free Run Timer 1 Free Run Timer 2 Free Run Timer 3 0000CCH 0000D0H EIRR0(R/W) B, H, W ENIR0(R/W) B, H, W 00000000 00000000 TCDT0(R/W) H, W 00000000 00000000 TCDT1(R/W) H, W 00000000 00000000 TCDT2(R/W) H, W 00000000 00000000 TCDT3(R/W) H, W 00000000 00000000 IPCP1 (R) H, W XXXXXXXX XXXXXXXX -- IPCP3 (R) H, W XXXXXXXX XXXXXXXX -- IPCP5 (R) H, W XXXXXXXX XXXXXXXX -- IPCP7 (R) H, W XXXXXXXX XXXXXXXX -- ELVR0(R/W) B, H, W 00000000 00000000 TCCS0(R/W) B, H, W 00000000 TCCS1(R/W) B, H, W 00000000 TCCS2(R/W) B, H, W 00000000 TCCS3(R/W) B, H, W 00000000 0000D4H -- 0000D8H -- 0000DCH -- 0000E0H -- 0000E4H IPCP0 (R) H, W XXXXXXXX XXXXXXXX ICS01 (R/W) B, H, W 00000000 IPCP2 (R) H, W XXXXXXXX XXXXXXXX ICS23 (R/W) B, H, W 00000000 IPCP4 (R) H, W XXXXXXXX XXXXXXXX ICS45 (R/W) B, H, W 00000000 IPCP6 (R) H, W XXXXXXXX XXXXXXXX ICS67 (R/W) B, H, W 00000000 0000E8H Input Capture 0, 1 0000ECH 0000F0H Input Capture 2, 3 0000F4H 0000F8H Input Capture 4, 5 0000FCH 000100H Input Capture 6, 7 (Continued) 26 MB91210 Series Address 000104H 000108H 00010CH 000110H 000114H 000118H 00011CH 000120H to 000140H 000144H 000148H 00014CH 000150H 000154H Register +0 +1 +2 +3 Block Reserved -- OCCP1(R/W) H, W XXXXXXXX XXXXXXXX OCCP3(R/W) H, W XXXXXXXX XXXXXXXX OCS23(R/W) B, H, W 11101100 00001100 OCCP5(R/W) H, W XXXXXXXX XXXXXXXX OCCP7(R/W) H, W XXXXXXXX XXXXXXXX OCS67(R/W) B, H, W 11101100 00001100 -- -- -- WTHR(R/W) B, H ---XXXXX WTDBL(R/W) B ------00 WTBR2(R/W) B ---XXXXX WTMR(R/W) B, H --XXXXXX WTCR(R/W) B, H 00000000 000-00-0 WTBR1(R/W) B XXXXXXXX WTSR(R/W) B --XXXXXX WTBR0(R/W) B XXXXXXXX -- OCCP0(R/W) H, W XXXXXXXX XXXXXXXX OCCP2(R/W) H, W XXXXXXXX XXXXXXXX OCS01(R/W) B, H, W 11101100 00001100 OCCP4(R/W) H, W XXXXXXXX XXXXXXXX OCCP6(R/W) H, W XXXXXXXX XXXXXXXX OCS45(R/W) B, H, W 11101100 00001100 Output Compare 0, 1 Output Compare 2, 3 Output Compare Cntl 0 to Cntl 3 Output Compare 4, 5 Output Compare 6, 7 Output Compare Cntl 4 to Cntl 7 Reserved Real-Time Clock ADERH(R/W) B, H, W 00000000 00000000 ADCS1(R/W) B, H, W 00000000 ADCT1(R/W) B, H, W 00010000 -- ADCS0(bit7-5:R/W bit4-0:R) B, H, W 00000000 ADCT0(R/W) B, H, W 00101100 CUCR(bit7, 6, 5, 3:R bit4, 2, 1, 0:R/ W) B, H, W 00000000 ADERL(R/W) B, H, W 00000000 00000000 ADCR1 (R) B, H, W ------XX ADSCH(R/W) B, H, W ---00000 ADCR0(bit7-5:R/W bit4-0:R) B, H, W XXXXXXXX ADECH(R/W) B, H, W ---00000 A/D Converter 000158H 00015CH CUTD (R/W) B, H, W 10000000 00000000 CUTR2 (R) B, H, W 00000000 00000000 -- Sub Clock Calibration unit 000160H 000164H to 0001A4H 0001A8H CUTR1 (R) B, H, W 00000000 00000000 Reserved Select CAN Clock Prescaler external interrupt (Continued) 27 CANPRE(bit7-4:R bit3-0:R/W) B, H, W 00000000 -- EISSR(R/W) B, H, W 00000000 00000000 MB91210 Series Address 0001ACH 0001B0H Register +0 +1 +2 +3 Block Reserved -- PRLH0(R/W) B, H, W XXXXXXXX PRLH2(R/W) B, H, W XXXXXXXX PPGC0(R/W) B, H, W 0000000X PRLH4(R/W) B, H, W XXXXXXXX PRLH6(R/W) B, H, W XXXXXXXX PPGC4(R/W) B, H, W 0000000X PRLH8(R/W) B, H, W XXXXXXXX PRLHA(R/W) B, H, W XXXXXXXX PPGC8(R/W) B, H, W 0000000X PRLHC(R/W) B, H, W XXXXXXXX PRLHE(R/W) B, H, W XXXXXXXX PPGCC(R/W) B, H, W 0000000X PRLL0(R/W) B, H, W XXXXXXXX PRLL2(R/W) B, H, W XXXXXXXX PPGC1(R/W) B, H, W 0000000X -- PRLL4(R/W) B, H, W XXXXXXXX PRLL6(R/W) B, H, W XXXXXXXX PPGC5(R/W) B, H, W 0000000X -- PRLL8(R/W) B, H, W XXXXXXXX PRLLA(R/W) B, H, W XXXXXXXX PPGC9(R/W) B, H, W 0000000X -- PRLLC(R/W) B, H, W XXXXXXXX PRLLE(R/W) B, H, W XXXXXXXX PPGCD(R/W) B, H, W 0000000X -- PRLHD(R/W) B, H, W XXXXXXXX PRLHF(R/W) B, H, W XXXXXXXX PPGCE(R/W) B, H, W 0000000X PRLLD(R/W) B, H, W XXXXXXXX PRLLF(R/W) B, H, W XXXXXXXX PPGCF(R/W) B, H, W 0000000X PRLH9(R/W) B, H, W XXXXXXXX PRLHB(R/W) B, H, W XXXXXXXX PPGCA(R/W) B, H, W 0000000X PRLL9(R/W) B, H, W XXXXXXXX PRLLB(R/W) B, H, W XXXXXXXX PPGCB(R/W) B, H, W 0000000X PRLH5(R/W) B, H, W XXXXXXXX PRLH7(R/W) B, H, W XXXXXXXX PPGC6(R/W) B, H, W 0000000X PRLL5(R/W) B, H, W XXXXXXXX PRLL7(R/W) B, H, W XXXXXXXX PPGC7(R/W) B, H, W 0000000X PRLH1(R/W) B, H, W XXXXXXXX PRLH3(R/W) B, H, W XXXXXXXX PPGC2(R/W) B, H, W 0000000X PRLL1(R/W) B, H, W XXXXXXXX PRLL3(R/W) B, H, W XXXXXXXX PPGC3(R/W) B, H, W 0000000X 0001B4H PPG 0 to PPG 3 0001B8H 0001BCH 0001C0H Reserved 0001C4H PPG 4 to PPG 7 0001C8H 0001CCH 0001D0H Reserved 0001D4H PPG 8 to PPG B 0001D8H 0001DCH 0001E0H Reserved 0001E4H PPG C to PPG F 0001E8H 0001ECH Reserved (Continued) 28 MB91210 Series Address Register +0 +1 +2 +3 Block PPG 0 to PPG F AP/INV 0001F0H 0001F4H to 0001FCH 000200H TRG1(R/W) B, H, W 00000000 TRG0(R/W) B, H, W 00000000 -- REVC1(R/W) B, H, W 00000000 REVC0(R/W) B, H, W 00000000 Reserved The lower 16 bits (DTC[15:0]) of DMACA0 (R/W) B, H, W, cannot be accessed as bytes. 00000000 00000000 00000000 00000000 DMACB0(R/W) B, H, W 00000000 00000000 00000000 00000000 The lower 16 bits (DTC[15:0]) of DMACA1 (R/W) B, H, W, cannot be accessed as bytes. 00000000 00000000 00000000 00000000 DMACB1(R/W) B, H, W 00000000 00000000 00000000 00000000 The lower 16 bits (DTC[15:0]) of DMACA2 (R/W) B, H, W, cannot be accessed as bytes. 00000000 00000000 00000000 00000000 DMACB2(R/W) B, H, W 00000000 00000000 00000000 00000000 The lower 16 bits (DTC[15:0]) of DMACA3 (R/W) B, H, W, cannot be accessed as bytes.00000000 00000000 00000000 00000000 DMACB3(R/W) B, H, W 00000000 00000000 00000000 00000000 The lower 16 bits (DTC[15:0]) of DMACA4 (R/W) B, H, W, cannot be accessed as bytes. 00000000 00000000 00000000 00000000 DMACB4(R/W) B, H, W 00000000 00000000 00000000 00000000 -- DMACR(bit31, 28-24:R/W bit30, 29, 23-0:R) B 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX -- Reserved DMAC DMAC 000204H 000208H 000210H 000214H 000218H 00021CH 000220H 000224H 000228H 00022CH to 00023CH 000240H 000244H to 0003ECH DMAC Reserved (Continued) 29 MB91210 Series Address 0003F0H 0003F4H 0003F8H 0003FCH Register +0 +1 +2 +3 Block BSD0 (W) W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 (R/W) W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC (W) W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR (R) W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDR0(R/W) B, H, W 00000000 DDR4(R/W) B, H, W 00000000 DDR8(R/W) B, H, W --000000 DDRC(R/W) B, H, W 00000000 DDR1(R/W) B, H, W 00000000 DDR5(R/W) B, H, W 00000000 DDR9(R/W) B, H, W 00000000 DDRD(R/W) B, H, W 00000000 -- PFR0(R/W) B, H, W 0000-00PFR4(R/W) B, H, W 00000000 PFR8(R/W) B, H, W 000----PFRC(R/W) B, H, W -------PFR1(R/W) B, H, W 00-00-0PFR5(R/W) B, H, W -0000000 PFR9(R/W) B, H, W 00000000 PFRD(R/W) B, H, W 00-00-0-- PFR2(R/W) B, H, W 00000000 PFR6(R/W) B, H, W ------00 PFRA(R/W) B, H, W -----000 PFRE(R/W) B, H, W -----00PFR3(R/W) B, H, W -------PFR7(R/W) B, H, W 00000-0PFRB(R/W) B, H, W -------PFRF(R/W) B, H, W -------Reserved (Continued) DDR2(R/W) B, H, W 00000000 DDR6(R/W) B, H, W ---00000 DDRA(R/W) B, H, W 00000000 DDRE(R/W) B, H, W -----000 DDR3(R/W) B, H, W 00000000 DDR7(R/W) B, H, W 00000000 DDRB(R/W) B, H, W 00000000 DDRF(R/W) B, H, W 00000000 Reserved Bit Search Module 000400H 000404H Data Direction Register 000408H 00040CH 000410H to 00041CH 000420H 000424H Port Function Register 000428H 00042CH 000430H to 00043CH 30 MB91210 Series Address Register +0 +1 +2 +3 Block 000440H ICR00(bit4:R bit30:R/W) B, H, W ---11111 ICR04(bit4:R bit30:R/W) B, H, W ---11111 ICR08(bit4:R bit30:R/W) B, H, W ---11111 ICR12(bit4:R bit30:R/W) B, H, W ---11111 ICR16(bit4:R bit30:R/W) B, H, W ---11111 ICR20(bit4:R bit30:R/W) B, H, W ---11111 ICR24(bit4:R bit30:R/W) B, H, W ---11111 ICR28(bit4:R bit30:R/W) B, H, W ---11111 ICR32(bit4:R bit30:R/W) B, H, W ---11111 ICR36(bit4:R bit30:R/W) B, H, W ---11111 ICR40(bit4:R bit30:R/W) B, H, W ---11111 ICR44(bit4:R bit30:R/W) B, H, W ---11111 ICR01(bit4:R bit30:R/W) B, H, W ---11111 ICR05(bit4:R bit30:R/W) B, H, W ---11111 ICR09(bit4:R bit30:R/W) B, H, W ---11111 ICR13(bit4:R bit30:R/W) B, H, W ---11111 ICR17(bit4:R bit30:R/W) B, H, W ---11111 ICR21(bit4:R bit30:R/W) B, H, W ---11111 ICR25(bit4:R bit30:R/W) B, H, W ---11111 ICR29(bit4:R bit30:R/W) B, H, W ---11111 ICR33(bit4:R bit30:R/W) B, H, W ---11111 ICR37(bit4:R bit30:R/W) B, H, W ---11111 ICR41(bit4:R bit30:R/W) B, H, W ---11111 ICR45(bit4:R bit30:R/W) B, H, W ---11111 -- ICR02(bit4:R bit30:R/W) B, H, W ---11111 ICR06(bit4:R bit30:R/W) B, H, W ---11111 ICR10(bit4:R bit30:R/W) B, H, W ---11111 ICR14(bit4:R bit30:R/W) B, H, W ---11111 ICR18(bit4:R bit30:R/W) B, H, W ---11111 ICR22(bit4:R bit30:R/W) B, H, W ---11111 ICR26(bit4:R bit30:R/W) B, H, W ---11111 ICR30(bit4:R bit30:R/W) B, H, W ---11111 ICR34(bit4:R bit30:R/W) B, H, W ---11111 ICR38(bit4:R bit30:R/W) B, H, W ---11111 ICR42(bit4:R bit30:R/W) B, H, W ---11111 ICR46(bit4:R bit30:R/W) B, H, W ---11111 ICR03(bit4:R bit30:R/W) B, H, W ---11111 ICR07(bit4:R bit30:R/W) B, H, W ---11111 ICR11(bit4:R bit30:R/W) B, H, W ---11111 ICR15(bit4:R bit30:R/W) B, H, W ---11111 ICR19(bit4:R bit30:R/W) B, H, W ---11111 ICR23(bit4:R bit30:R/W) B, H, W ---11111 ICR27(bit4:R bit30:R/W) B, H, W ---11111 ICR31(bit4:R bit30:R/W) B, H, W ---11111 ICR35(bit4:R bit30:R/W) B, H, W ---11111 ICR39(bit4:R bit30:R/W) B, H, W ---11111 ICR43(bit4:R bit30:R/W) B, H, W ---11111 ICR47(bit4:R bit30:R/W) B, H, W ---11111 Reserved (Continued) Interrupt Control Unit Interrupt Control Unit 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H to 00047CH 31 MB91210 Series Address Register +0 +1 +2 +3 Block 000480H RSRR(bit15-10:R bit9, 8:R/W) B, H, W X*****00 CLKR(R/W) B, H, W 00000000 -- STCR(R/W) B, H, W 00110011(*: depends on source) WPR(W) B, H, W XXXXXXXX TBCR(bit15-10:R/ W bit9, 8:R) B, H, W 00XXXX11 DIVR0(R/W) B, H, W 00000000 OSCCR(R/W) B XXXXXXX0 -- CTBR(W) B, H, W XXXXXXXX DIVR1(R/W) B, H, W 00000000 -- Reserved -- Oscillation Stabilization Wait Time Reserved Clock Control Unit 000484H 000488H 00048CH 000490H 000470H to 00047CH 000500H PPER0(R/W) B, H, W 00000000 PPER4(R/W) B, H, W 00000000 PPER8(R/W) B, H, W --000000 PPERC(R/W) B, H, W 00000000 OSCCR(bit15-9:R/W bit8:W) B 000XX000 XXXXXXXX -- PPER1(R/W) B, H, W 00000000 PPER5(R/W) B, H, W 00000000 PPER9(R/W) B, H, W 00000000 PPERD(R/W) B, H, W 00000000 -- PPER2(R/W) B, H, W 00000000 PPER6(R/W) B, H, W ---00000 PPERA(R/W) B, H, W 00000000 PPERE(R/W) B, H, W -----000 PPER3(R/W) B, H, W 00000000 PPER7(R/W) B, H, W 00000000 PPERB(R/W) B, H, W 00000000 PPERF(R/W) B, H, W 00000000 Reserved (Continued) 000504H Port Pull-down Select Register 000508H 00050CH 000510H to 00051CH 32 MB91210 Series Address Register +0 +1 +2 +3 Block 000520H PPCR0(R/W) B, H, W 11111111 PPCR4(R/W) B, H, W 11111111 PPCR8(R/W) B, H, W --111111 PPCRC(R/W) B, H, W 11111111 PPCR1(R/W) B, H, W 11111111 PPCR5(R/W) B, H, W 11111111 PPCR9(R/W) B, H, W 11111111 PPCRD(R/W) B, H, W 11111111 -- PPCR2(R/W) B, H, W 11111111 PPCR6(R/W) B, H, W ---11111 PPCRA(R/W) B, H, W 11111111 PPCRE(R/W) B, H, W -----111 PPCR3(R/W) B, H, W 11111111 PPCR7(R/W) B, H, W 11111111 PPCRB(R/W) B, H, W 11111111 PPCRF(R/W) B, H, W 11111111 Reserved 000524H Port Pull-down Control Register 000528H 00052CH 000530H to 00053CH 000540H PILR0(R/W) B, H, W 00000000 PILR4(R/W) B, H, W 00000000 PILR8(R/W) B, H, W --000000 PILRC(R/W) B, H, W --000000 PILR1(R/W) B, H, W 00000000 PILR5(R/W) B, H, W 00000000 PILR9(R/W) B, H, W 00000000 PILRD(R/W) B, H, W 00000000 -- -- -- PILR2(R/W) B, H, W 00000000 PILR6(R/W) B, H, W ---00000 PILRA(R/W) B, H, W 00000000 PILRE(R/W) B, H, W -----000 PILR3(R/W) B, H, W 00000000 PILR7(R/W) B, H, W 00000000 PILRB(R/W) B, H, W 00000000 PILRF(R/W) B, H, W 00000000 Port Input Level Select Register Reserved Reserved Reserved (Continued) Port Input Level Select Register 000544H 000548H 00054CH 000550H to 000574H 000578H 00057CH to 00061CH 33 MB91210 Series Address 000620H 000624H Register +0 +1 +2 +3 Block PIDR0 (R) B, H, W PIDR1 (R) B, H, W PIDR2 (R) B, H, W PIDR3 (R) B, H, W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PIDR4 (R) B, H, W PIDR5 (R) B, H, W PIDR6 (R) B, H, W PIDR7 (R) B, H, W XXXXXXXX XXXXXXXX --XXXXXX XXXXXXXX Input Data Direct PIDR8 (R) B, H, W PIDR9 (R) B, H, W PIDRA (R) B, H, W PIDRB (R) B, H, W Read Register 000628H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00062CH 000630H to 000FFCH 001000H 001004H 001008H 00100CH 001010H 001014H 001018H 00101CH PIDRC (R) B, H, W PIDRD (R) B, H, W PIDRE (R) B, H, W PIDRF (R) B, H, W XXXXXXXX XXXXXXXX -----XXX XXXXXXXX -- DMASA0(R/W) W 00000000 00000000 00000000 00000000 DMADA0(R/W) W 00000000 00000000 00000000 00000000 DMASA1(R/W) W 00000000 00000000 00000000 00000000 DMADA1(R/W) W 00000000 00000000 00000000 00000000 DMASA2(R/W) W 00000000 00000000 00000000 00000000 DMADA2(R/W) W 00000000 00000000 00000000 00000000 DMASA3(R/W) W 00000000 00000000 00000000 00000000 DMADA3(R/W) W 00000000 00000000 00000000 00000000 (Continued) Reserved DMA Controller 34 MB91210 Series Address 001020H 001024H 001028H to 006FFCH 007000H Register +0 +1 +2 +3 Block DMASA4(R/W) W 00000000 00000000 00000000 00000000 DMADA4(R/W) W 00000000 00000000 00000000 00000000 -- FLCR(bit7-3:R bit2-0:R/W) B, H, W 0000X101 FLWC(R/W) B, H, W 01011011 -- CTRLR0(bit15-8:R bit7-0:R/W) B, H, W STATR0(bit15-5:R bit4-0:R/W) B, H, W 00000000 00000001 00000000 00000000 ERRCNT0 (R) B, H, W 00000000 00000000 INTR0 (R) B, H, W 00000000 00000000 BRPER0(bit15-4:R bit4-0:R/W) B, H, W 00000000 00000000 IF1CREQ0(bit15, 7-0:R/W bit14-8:R) B, H, W 00000000 00000001 IF1MSK20(R/W) B, H, W 11111111 11111111 IF1ARB20(R/W) B, H, W 00000000 00000000 IF1MCTR0(bit15-7, 3-0:R/W bit6-4:R) B, H, W 00000000 00000000 IF1DTA10(R/W) B, H, W 00000000 00000000 IF1DTB10(R/W) B, H, W 00000000 00000000 BTR0(bit15, 11-8:R bit14-12, 7-0:R/W) B, H, W 00100011 00000001 TESTR0(bit15-7, 1, 0:R bit6-2:R/W) B, H, W 00000000 r0000000 (r : indication the level on the CAN bus) -- IF1CMSK0(bit15-8:R bit7-0:R/W) B, H, W 00000000 00000000 IF1MSK10(R/W) B, H, W 11111111 11111111 IF1ARB10(R/W) B, H, W 00000000 00000000 -- IF1DTA20(R/W) B, H, W 00000000 00000000 IF1DTB20(R/W) B, H, W 00000000 00000000 DMA Controller Reserved -- Flash Interface -- 007004H 007008H to 01FFFCH 020000H 020004H Reserved 020008H CAN Controller 0 02000CH 020010H 020014H 020018H 02001CH 020020H 020024H CAN Controller 0 (Continued) 35 MB91210 Series Address 020028H to 02003CH 020040H Register +0 +1 +2 +3 Block -- IF2CREQ0(bit15, 7-0:R/W bit14-8:R) B, H, W 00000000 00000001 IF2MSK20(R/W) B, H, W 11111111 11111111 IF2ARB20(R/W) B, H, W 00000000 00000000 IF2MCTR0(bit15-7, 3-0:R/W bit6-4:R) B, H, W 00000000 00000000 IF2DTA10(R/W) B, H, W 00000000 00000000 IF2DTB10(R/W) B, H, W 00000000 00000000 -- TREQR20 (R) B, H, W 00000000 00000000 TREQR10 (R) B, H, W 00000000 00000000 -- NEWDT20 (R) B, H, W 00000000 00000000 -- INTPND20 (R) B, H, W 00000000 00000000 -- MSGVAL20 (R) B, H, W 00000000 00000000 -- MSGVAL10 (R) B, H, W 00000000 00000000 INTPND10 (R) B, H, W 00000000 00000000 NEWDT10 (R) B, H, W 00000000 00000000 IF2CMSK0(bit15-8:R bit7-0:R/W) B, H, W 00000000 00000000 IF2MSK10(R/W) B, H, W 11111111 11111111 IF2ARB10(R/W) B, H, W 00000000 00000000 -- IF2DTA20(R/W) B, H, W 00000000 00000000 IF2DTB20(R/W) B, H, W 00000000 00000000 Reserved 020044H 020048H CAN Controller 0 02004CH 020050H 020054H 020058H to 02007CH 020080H 020084H to 02008CH 020090H 020094H to 02009CH 0200A0H 0200A4H to 0200ACH 0200B0H 0200B4H to 0200FCH Reserved -- -- CAN Controller 0 Reserved CAN Controller 0 Reserved CAN Controller 0 Reserved CAN Controller 0 Reserved (Continued) 36 MB91210 Series Address 020100H Register +0 +1 +2 +3 Block CTRLR1(bit15-8:R bit7-0:R/W) B, H, W STATR1(bit15-5:R bit4-0:R/W) B, H, W 00000000 00000001 00000000 00000000 ERRCNT1 (R) B, H, W 00000000 00000000 BTR1(bit15, 11-8:R bit14-12, 7-0:R/W) B, H, W 00100011 00000001 TESTR1(bit15-7, 1, 0:R bit6-2:R/W) B, H, W 00000000 r0000000 (r : indication the level on the CAN bus) -- IF1CMSK1(bit15-8:R bit7-0:R/W) B, H, W 00000000 00000000 IF1MSK1(R/W) B, H, W 11111111 11111111 IF1ARB11(R/W) B, H, W 00000000 00000000 -- IF1DTA21(R/W) B, H, W 00000000 00000000 IF1DTB21(R/W) B, H, W 00000000 00000000 -- IF2CREQ1(bit15, 7-0:R/W bit14-8:R) B, H, W 00000000 00000001 IF2MSK21(R/W) B, H, W 11111111 11111111 IF2ARB21(R/W) B, H, W 00000000 00000000 IF2MCTR1(bit15-7, 3-0:R/W bit6-4:R) B, H, W 00000000 00000000 IF2DTA11(R/W) B, H, W 00000000 00000000 IF2DTB11(R/W) B, H, W 00000000 00000000 IF2CMSK1(bit15-8:R bit7-0:R/W) B, H, W 00000000 00000000 IF2MSK11(R/W) B, H, W 11111111 11111111 IF2ARB11(R/W) B, H, W 00000000 00000000 -- IF2DTA21(R/W) B, H, W 00000000 00000000 IF2DTB21(R/W) B, H, W 00000000 00000000 CAN Controller 1 (Continued) 37 CAN Controller 1 Reserved 020104H 020108H INTR1 (R) B, H, W 00000000 00000000 BRPER1(bit15-4:R bit4-0:R/W) B, H, W 00000000 00000000 IF1CREQ1(bit15, 7-0:R/W bit14-8:R) B, H, W 00000000 00000001 IF1MSK21(R/W) B, H, W 11111111 11111111 IF1ARB21(R/W) B, H, W 00000000 00000000 IF1MCTR1(bit15-7, 3-0:R/W bit6-4:R) B, H, W 00000000 00000000 IF1DTA11(R/W) B, H, W 00000000 00000000 IF1DTB11(R/W) B, H, W 00000000 00000000 02010CH 020110H CAN Controller 1 020114H 020118H 02011CH 020120H 020124H 020128H to 02013CH 020140H 020144H 020148H 02014CH 020150H 020154H MB91210 Series Register +0 +1 +2 +3 Address 020158H to 02017CH 020180H 020184H to 02018CH 020190H 020194H to 02019CH 0201A0H 0201A4H to 0201ACH 0201B0H 0200B4H to 0200FCH 020200H Block -- TREQR21 (R) B, H, W 00000000 00000000 -- NEWDT21 (R) B, H, W 00000000 00000000 -- INTPND21 (R) B, H, W 00000000 00000000 -- MSGVAL21 (R) B, H, W 00000000 00000000 -- CTRLR2(bit15-8:R bit7-0:R/W) B, H, W STATR2(bit15-5:R bit4-0:R/W) B, H, W 00000000 00000001 00000000 00000000 ERRCNT2 (R) B, H, W 00000000 00000000 BTR2(bit15, 11-8:R bit14-12, 7-0:R/W) B, H, W 00100011 00000001 TESTR2(bit15-7, 1, 0:R bit6-2:R/W) B, H, W 00000000 r0000000 (r : indication the level on the CAN bus) -- IF1CMSK2(bit15-8:R bit7-0:R/W) B, H, W 00000000 00000000 IF1MSK12(R/W) B, H, W 11111111 11111111 IF1ARB12(R/W) B, H, W 00000000 00000000 -- MSGVAL11 (R) B, H, W 00000000 00000000 INTPND11 (R) B, H, W 00000000 00000000 NEWDT11 (R) B, H, W 00000000 00000000 TREQR11 (R) B, H, W 00000000 00000000 Reserved CAN Controller 1 Reserved CAN Controller 1 Reserved CAN Controller 1 Reserved CAN Controller 1 Reserved 020204H 020208H INTR2 (R) B, H, W 00000000 00000000 BRPER2(bit15-4:R bit4-0:R/W) B, H, W 00000000 00000000 IF1CREQ2(bit15, 7-0:R/W bit14-8:R) B, H, W 00000000 00000001 IF1MSK22(R/W) B, H, W 11111111 11111111 IF1ARB22(R/W) B, H, W 00000000 00000000 IF1MCTR2(bit15-7, 3-0:R/W bit6-4:R) B, H, W 00000000 00000000 02020CH CAN Controller 2 020210H 020214H 020218H 02021CH (Continued) 38 MB91210 Series (Continued) Address 020220H 020224H 020228H to 02023CH 020240H IF2CREQ2(bit15, 7-0:R/W bit14-8:R) B, H, W 00000000 00000001 IF2MSK22(R/W) B, H, W 11111111 11111111 -- CAN Controller 2 IF2MCTR2(bit15-7, 3-0:R/W bit6-4:R) B, H, W 00000000 00000000 IF2DTA12(R/W) B, H, W 00000000 00000000 IF2DTB12(R/W) B, H, W 00000000 00000000 -- TREQR22 (R) B, H, W 00000000 00000000 -- NEWDT22 (R) B, H, W 00000000 00000000 -- INTPND22 (R) B, H, W 00000000 00000000 -- MSGVAL22 (R) B, H, W 00000000 00000000 MSGVAL12 (R) B, H, W 00000000 00000000 INTPND12 (R) B, H, W 00000000 00000000 NEWDT12 (R) B, H, W 00000000 00000000 TREQR12 (R) B, H, W 00000000 00000000 -- IF2DTA22(R/W) B, H, W 00000000 00000000 IF2DTB22(R/W) B, H, W 00000000 00000000 Reserved Register +0 +1 +2 +3 Block IF1DTA12(R/W) B, H, W 00000000 00000000 IF1DTB12(R/W) B, H, W 00000000 00000000 -- IF1DTA22(R/W) B, H, W 00000000 00000000 IF1DTB22(R/W) B, H, W 00000000 00000000 CAN Controller 2 Reserved IF2CMSK2(bit15-8:R bit7-0:R/W) B, H, W 00000000 00000000 IF2MSK12(R/W) B, H, W 11111111 11111111 020244H 020248H to 02024BH 02024CH 020250H 020254H 020258H to 02027CH 020280H 020284H to 02028CH 020290H 020294H to 02029CH 0202A0H 0202A4H to 0202ACH 0202B0H CAN Controller 2 Reserved CAN Controller 2 Reserved CAN Controller 2 Reserved CAN Controller 2 39 MB91210 Series INTERRUPT VECTOR Interrupt number Interrupt source Reset*1 Mode vector*1 System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (ICE) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* 2 2 2 Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Hexadecimal 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 Interrupt level -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15(FH) Fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH 378H 374H 370H TBR default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH 000FFF78H 000FFF74H 000FFF70H (Continued) Maskable interrupt source*2 Maskable interrupt source*2 Maskable interrupt source*2 Maskable interrupt source*2 Maskable interrupt source* Maskable interrupt source* 2 2 40 MB91210 Series Interrupt number Interrupt source Maskable interrupt source*2 Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Timebase timer overflow Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Maskable interrupt source* Delay interrupt source bit System reserved (Used by REALOS) System reserved (Used by REALOS) System reserved System reserved System reserved System reserved System reserved System reserved 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Decimal 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Hexadecimal 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 Interrupt level ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47 -- -- -- -- -- -- -- -- Offset 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H TBR default address 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H (Continued) 41 MB91210 Series (Continued) Interrupt number Interrupt source System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used in INT instruction Decimal 72 73 74 75 76 77 78 79 80 to 255 Hexadecimal 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interrupt level -- -- -- -- -- -- -- -- -- Offset 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H TBR default address 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H *1: Even though the TBR value is changed, fixed addresses, 000FFFFCH and 000FFFF8H, are always used for the reset vector and the mode vector. *2: The maskable interrupt source is defined for each model. 42 MB91210 Series PIN STATUS IN EACH CPU STATE Terms used as the status of pins mean as follows. * Input enabled Indicates that the input function can be used. * Output Hi-Z Means the placing of a pin in a high impedance state by preventing the transistor for driving the pin from driving. * Output maintained Indicates the output in the output state existing immediately before this mode is established. If the device enters this mode with an internal output peripheral operating or while serving as an output port, the output is performed by the internal peripheral or the port output is maintained, respectively. * State existing immediately before is maintained. When the device serves for output or input immediately before entering this mode, the device maintains the output or is ready for the input, respectively. 43 MB91210 Series TABLE OF PIN STATUS IN EACH MODE * Single chip mode Initial value Pin name Function name In sleep state INITX = "L" INITX = "H" INITX X0 X1 X0A X1A MD0 MD1 MD2 MD3 P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 P15 P16 P17 INITX X0 X1 X0A X1A MD0 MD1 MD2 MD3 P00/SIN5/INT8R P01/SOT5/INT9R P02/SCK5/INT10R P03/SIN6/INT11R P04/SOT6/INT12R P05/SCK6/INT13R P06/OUT4/INT14R P07/OUT5/INT15R P10/TIN1 P11/TOT1 P12/SIN3 P13/SOT3 P14/SCK3 P15/SIN4 P16/SOT4 P17/SCK4 Output Hi-Z input enabled Output Hi-Z input enabled P: Immediately preceding status held F: Normal operation performed P: Immediately preceding status held F: Output held or Hi-Z , input enabled Output Hi-Z internal input held Output Hi-Z/ selecting interrupt function, and input enabled when interrupt is allowed during ENIR internal input held Input enabled Input enabled Input enabled Input enabled Input enabled In stop state HIZ = 0 Input enabled Hi-Z or input enabled "H" output or input enabled Hi-Z or input enabled "H" output or input enabled HIZ = 1 Input enabled Hi-Z or input enabled "H" output or input enabled Hi-Z or input enabled "H" output or input enabled P20 to P27/ P20 to P27 PPG0, 2, 4, 6, 8, A, C, E (Continued) 44 MB91210 Series Pin name Function name Initial value INITX = "L" INITX = "H" In sleep state In stop state HIZ = 0 HIZ = 1 Output Hi-Z/ selecting interrupt function, and input enabled when interrupt is allowed during ENIR internal input held Output Hi-Z internal input held Output Hi-Z/ selecting interrupt function, and input enabled when interrupt is allowed during ENIR internal input held P30 P30/ (RX2) / (INT10C) P31 P32 P31/ (TX2) P32/INT10 P33 to P37 P33 to P37/ INT11 to INT15 P40 to P43 P44 to P47 P50 to P53 P54 P55 P56 P57 P60 P61 P62 P63 P64 P40 to P43/ PPG9, B, D, F P44 to P47/ IN0 to IN3 P50 to P53/ PPG1, 3, 5, 7 P54/IN4 P55/IN5 P56/IN6 P57/IN7 P60/OUT6 P61/OUT7 P62 P63 P64 Output Hi-Z/ selecting interrupt function, and input enabled when interrupt is allowed during ENIR internal input held Output Hi-Z internal input held (Continued) Output Hi-Z input enabled Output Hi-Z input enabled P: Immediately preceding status held F: Normal operation performed P: Immediately preceding status held F: Output held or Hi-Z , input enabled Output Hi-Z internal input held P70 P70/RX0/INT8 P71 P71/TX0 45 MB91210 Series Pin name Function name Initial value INITX = "L" INITX = "H" In sleep state In stop state HIZ = 0 HIZ = 1 Output Hi-Z/ selecting interrupt function, and input enabled when interrupt is allowed during ENIR internal input held P72 P72/RX1/INT9 P73 P74 to P77 P80 to P83 P84 P85 P90 to P97 PA0 PA1 PA2 PA3 to PA7 P73/TX1 P74 to P77/ OUT0 to OUT3 P80 to P83/ FRCK0 to FRCK3 P84/TIN2 P85/TOT2 P90 to P97/PPG0R, 2R, ER/AN0 to AN7 PA0/SIN2R/AN8 PA1/SOT2R/AN9 PA2/SCK2R/AN10 PA3 to PA7/ AN11 to AN15 Output Hi-Z/ selecting interrupt function, and input enabled when interrupt is allowed during ENIR internal input held Output Hi-Z internal input held (Continued) Output Hi-Z input enabled Output Hi-Z input enabled P: Immediately preceding status held F: Normal operation performed P: Immediately preceding status held F: Output held or Hi-Z , input enabled Output Hi-Z internal input held Output Hi-Z internal input held PB0 to PB7 PB0 to PB7/ INT0R to INT7R/ AN16 to AN23 PC0 to PC7 PC0 to PC7/ AN24 to AN31 46 MB91210 Series (Continued) Pin name PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0 PE1 PE2 Function name PD0/TIN0/ATGX PD1/TOT0 PD2/SIN0 PD3/SOT0 PD4/SCK0 PD5/SIN1 PD6/SOT1 PD7/SCK1 PE0/SIN2 PE1/SOT2 PE2/SCK2 Output Hi-Z input enabled Output Hi-Z input enabled P: Immediately preceding status held F: Normal operation performed P: Immediately preceding status held F: Output held or Hi-Z , input enabled Output Hi-Z internal input held Initial value INITX = "L" INITX = "H" In sleep state In stop state HIZ = 0 HIZ = 1 PF0 to PF7 PF0 to PF7/ INT0 to INT7 Output Hi-Z/ selecting interrupt function, and input enabled when interrupt is allowed during ENIR internal input held 47 MB91210 Series ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Parameter Symbol VCC Power supply voltage Input voltage Output voltage Maximum clamp current Total maximum clamp current "L" level maximum output current* "L" level average output current*3 "L" level total maximum output current "L" level total average output current* "H" level maximum output current* "H" level average output current*3 "H" level total maximum output current "H" level total average output current* Power consumption Operating temperature Storage temperature 4 2 4 2 Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 -- -- -- -- -- -- -- -- -- -- - 40 - 55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VCC + 0.3 VCC + 0.3 + 2.0 20 8 2 64 25 -8 -2 - 64 - 25 500 + 105 + 150 Unit V V V V V mA mA mA mA mA mA mA mA mA mA mW C C *5 *5 Remarks AVCC AVRH VI VO ICLAMP ICLAMP IOL1 IOLAV1 IOL1 IOLAV1 IOH1 IOHAV1 IOH1 IOHAV1 PD TA Tstg AVCC = VCC*1 AVCC AVRH Single-chip mode *1: Caution must be taken that AVCC does not exceed VCC upon power-on and under other circumstances. *2: The maximum output current defines the peak current value of each of the corresponding pins. *3: The average output current defines the average value of the current (100 ms) which passes through each of the corresponding pins. The average value represents a value calculated by multiplying the operating current by the operating rate. *4: The total average output current defines the average value of the current (100 ms) which passes through all the corresponding pins. The average value represents a value calculated by multiplying the operating current by the operating rate. *5: * Corresponding pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P64, P70 to P77, P80 to P85, P90 to P97, PA0 to PA7, PB0 to PB7, PC0 to PC7, PD0 to PD7, PE0 to PE2,PF0 to PF7 * Use within recommended operating conditions. * Use at DC voltage (current). * The + B signal should always be applied a limiting resistor placed between the + B signal and the microcontroller. * The value of the limiting resistor should be set so that when the + B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that, when the microcontroller drive current is low as in low power consumption mode, the + B input potential can increase the potential at the VCC pin via a protection diode, possibly affecting other devices. (Continued) 48 MB91210 Series (Continued) * Note that, if the + B input exists when the microcontroller is off (not fixed at 0 V), power is supplied through the pin, possibly causing the microcontroller to operate imperfectly. Note that, if the + B input exists when the power supply is turned on, power is supplied through the pin, possibly resulting in a power-supply voltage at which a power-on reset does not work. * Be careful not to let the + B input pin open. * Note that the analog I/O pins (such as the LCD drive and comparator input pins) other than the A/D input pin cannot input + B. * Recommended example circuit * Input/output equivalent circuits Protection diode VCC P-ch Limiting resistor + B Input (0 V to 16 V) N-ch R WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. 49 MB91210 Series 2. Recommended operation condition (VSS=AVSS=0.0 V) Parameter Symbol VCC AVCC VCC Value Min 3.5 3.0 Max 5.5 5.5 Unit V V F C Remarks Normal operation RAM data retention at STOP operation Use a ceramic capacitor or a capacitor with similar frequency characteristics. Use a bypass capacitor for the VCC pin, which has larger than CS. Single-chip mode Power supply voltage Smoothing capacitor* CS 1 (within tolerance 50%) - 40 + 105 Operating temperature TA * : For how to connect the smoothing capacitor CS, see the figure below. * C Pin Connection Diagram C CS VSS AVSS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 50 MB91210 Series 3. DC Specifications (TA: Recommended operating conditions; VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Symbol VIHS VIHC "H" level input voltage VIHM VIHI VILS VILC "L" level input voltage VILM VILI ICC ICCS ICCL ICCR32 ICCR4 ICCH Input leakage current Input capacity Pull-up resistance Pull-down resistance Output H voltage Output L voltage IIL CIN RUP RDOWN VOH VOL Pin name -- -- MD0 to MD3 INITX -- -- MD0 to MD3 INITX VCC VCC VCC VCC VCC VCC -- -- -- -- Condition -- -- -- -- -- -- -- -- *1 *2 *3 *4 *5 *6 Value Min 0.8 x VCC 0.7 x VCC VCC - 0.3 0.8 x VCC VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 -- -- -- -- -- -- -- -5 -- 25 25 Typ -- -- -- -- -- -- -- -- 40 2 28 150 80 800 70 -- 5 50 50 -- -- Max VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.5 x VCC 0.3 x VCC VSS + 0.3 0.2 x VCC 60 3 42 300 200 1200 150 +5 15 100 100 -- 0.4 Unit V V V V V V V V mA mA mA A A A A A pF k k V V All ports and INITX Exclusive of all Flash memory product All ports All ports Normal operation *7 PLL stop operation (2 MHz) SLEEP operation *7 Sub-operation *7 32 kHz clock operation 4 MHz clock operation STOP All input pins CMOS automotive input CMOS Schmitt input Remarks CMOS automotive input CMOS Schmitt input Power supply current IOH= - 2 mA VCC - 0.5 IOL=2 mA -- *1 : CLKB = 40 MHz, CLKP = 20 MHz, CLKT = 10 MHz, CANCLK = 10 MHz *2 : Under *2, CPU stopped. *3 : CLKB = CLKP = CLKT = CANCLK = 32 kHz, TA = + 25 C *4 : CPU/peripheral circuit operation stopped, main oscillation stopped, 32 kHz clock operation, TA = + 25 C *5 : CPU/peripheral circuit operation stopped, sub-oscillation stopped, 4 kHz clock operation, TA = + 25 C *6 : CPU/peripheral circuit operation stopped, all oscillation circuits stopped, TA = + 25 C *7 : The current consumption in normal operation/SLEEP mode, is the value at the maximum operation of the peripheral circuit. 51 MB91210 Series 4. AC Specifications (1) Clock timing (TA: Recommended operating conditions; VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Symbol Pin name Condition FC Frequency of source oscillation clock Source oscillation clock cycle time FCA tCYL tCYLL X0, X1 X0A, X1A X0, X1 X0A, X1A X0 -- Value Min -- -- -- 62.5 10 30 Typ 4 32.768 32.768 250 30.5 -- Max 16 100 -- -- -- -- Unit MHz kHz MB91F213 kHz MB91F211 ns s ns The duty ration normally ranges from 40% to 60%. When external clock is used Remarks Input clock pulse width PWH, PWL Input clock rise/ fall time Frequency of internal clock operation Internal operation clock cycle time tcr, tcf X0 -- -- 5 ns FCP -- -- -- 40 When main clock MHz and PLL clock is used. ns When main clock and PLL clock is used. tCP -- -- 25 -- -- tCYL 0.8 Vcc 0.2 Vcc PWH tcf PWL tcr X0 52 MB91210 Series * Operation guarantee range Relation between internal operation clock frequency and power supply voltage Recommended operation range Power supply voltage VCC (V) 5.5 4.0 3.5 PLL operation guarantee range 2 8 20 40 Internal operation clock FCP (MHz) Note : PLL operation stabilizing wait time should be set to 500 s or more. Relation between oscillation clock frequency and internal operation clock (example) Source oscillation (4 MHz) Divider Multiplier 1 2 4 6 8 10 1/2 FCP - - - - 32 MHz 40 MHz 1/4 FCP - - 16 MHz 24 MHz 32 MHz - 1/8 FCP - 8 MHz 16 MHz - - - Source oscillation (5 MHz) Divider Multiplier 1 2 4 6 8 10 1/2 FCP - - - - 40 MHz - 1/4 FCP - - 20 MHz 30 MHz - - 1/8 FCP - 10 MHz - - - - Source oscillation (10 MHz) Divider Multiplier 1 2 4 6 8 10 1/2 FCP - - 40 MHz - - - 1/4 FCP - 20 MHz - - - - 1/8 FCP 10 MHz - - - - - Source oscillation (16 MHz) Divider Multiplier 1 2 4 6 8 10 1/2 FCP - 32 MHz - - - - 1/4 FCP 16 MHz 32 MHz - - - - 1/8 FCP 16 MHz - - - - - -: Prohibited 53 MB91210 Series AC specifications are defined by the following measurement standard voltage values: Input signal waveform Hysteresis input pin 0.7 Vcc 0.3 Vcc Output signal waveform Output pin 4.6 V 0.4 V Hysteresis input pin (Automotive) 0.8 Vcc 0.5 Vcc Example oscillation circuit X0 X1 R C1 C2 54 MB91210 Series (2) Reset input (TA: Recommended operating conditions; VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Symbol Pin name Condition Value Min 500 tINTL INITX -- 217 x tCYL Max -- -- Unit ns ms Upon power-on and in stop mode Remarks INITX input time tINTL, INITX 0.2 Vcc 0.2 Vcc * In stop mode tINTL INITX 90% of amplitude 0.2 Vcc 0.2 Vcc X0 Internal operation clock Oscillation time of oscillator Oscillation stabilization wait time Internal reset Instruction executed 55 MB91210 Series [External reset input specifications (INITX) and internal reset signal cancellation timing] * When an external reset input is generated, a maximum of 256 tcp is designed to be spent until it reaches the internal reset signal to transmit all reset signals to the internal logic. (Max 8 s at 32 MHz) * The following chart shows how to set the timing for instruction execution start (start of application operation) after external reset input. Time from external reset input to instruction start = Max 256 tcp + 61 tcp * Timing Chart Min 500 ns INITX Internal reset input timing 61 tcp Max 256 tcp Internal reset Internal reset cancellation timing 56 MB91210 Series (3) Power-on Conditions (TA : Recommended operating conditions; VSS = 0.0 V) Value Parameter Power supply rising time Power supply start voltage Power supply peak voltage Power supply cut-off time Symbol Pin name Condition Min tR VOFF VON tOFF VCC -- 0.05 -- 3.5 50 Max 30 0.2 -- -- ms V V ms -- -- -- Due to repetitive operation Unit Remarks tR VCC 0.2 V 3.5 V 0.2 V t OFF 0.2 V (4) Power supply drop time, power supply voltages and external reset input to retain RAM data. Satisfy the following reset input standard to retain the RAM data used in the single chip mode. VCC(V) 3.5 V 3.0 V dropped Voltage drop time Min 256 tcp External reset input standard (INITX) Min 256 tcp Vcc 3.5 V 3.0 V 3.5 V 3.0 V INITX 256 tcp To retain RAM data, enter 256 tcp of INITX or more before dropping VCC to 3.0 V or lower. 57 MB91210 Series (5) UART Timing (TA: Recommended operating conditions; VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Symbol Pin name tSCYC tSLOV tIVSH tSHIX tSHSL SCK tSLSH tSLOV tIVSH tSHIX SCK SOT SCK SIN Output pin, CL = 30 pF + 1 x TTL 4 tCP -- 60 60 -- 150 -- -- ns ns ns ns For external shift clock mode SCK SCK SOT SCK SIN Output pin, CL = 30 pF + 1 x TTL Condition Value Min 8 tCP - 80 100 60 4 tCP Max -- + 80 -- -- -- Unit ns ns ns ns ns For internal shift clock mode Remarks Note: These are AC characteristics for CLK synchronous mode. CL is a load capacitance connected to pins during testing. 58 MB91210 Series * For internal shift clock mode tSCYC SCK 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH 0.7 VCC SIN 0.3 VCC tSHIX 0.7 VCC 0.3 VCC 2.4 V 0.8 V * For external shift clock mode tSLSH SCK 0.3 VCC tSLOV SOT 2.4 V 0.8 V tIVSH 0.7 VCC SIN 0.3 VCC tSHIX 0.7 VCC 0.3 VCC 0.3 VCC 0.7 VCC tSHSL 0.7 VCC 59 MB91210 Series (6) Timer Input Timing (TA: Recommended operating conditions; VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Input pulse width Symbol tTIWH tTIWL Pin name TIN0 to TIN2 IN0 to IN7 Condition -- Value Min 4 tCP Max -- Unit ns * Timer Input Timing tTIWH TINx INx 0.7 Vcc 0.7 Vcc 0.3 Vcc 0.3 Vcc tTIWL (7) External Interrupt Timing (TA: Recommended operating conditions; VCC = 5.0 V 10%, VSS = AVSS = 0.0 V) Parameter Input pulse width Symbol tINTH, tINTL Pin name INT0 to INT15 Condition Value Min 3 tCP Max -- Unit ns * External Interrupt Input Timing tINTH 0.8 VCC INTx 0.8 VCC tINTL 0.5 VCC 0.5 VCC 60 MB91210 Series 5. Flash Memory Write/Erase Characteristics Parameter Sector erase time Word write time Chip write time Erase/write cycle Data retention time Condition TA= + 25 C, VCC=5.0 V TA= + 25 C VCC=5.0 V TA= + 25 C, VCC=5.0 V Average TA= + 85 C Value Min -- -- -- 10000 20* Typ 0.5 6 3.4 -- -- Max 2.0 100 56 -- -- Unit s s s cycle year Remarks Exclusive of internal write time prior to erase Exclusive of overhead time at system level Exclusive of overhead time at system level *: This value comes from the technology qualification (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 C). 61 MB91210 Series 6. A/D Converter Electrical Characteristics (TA : Recommended operating conditions; VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V) Parameter Resolution Total error Non-liner error Differential linearity error Zero transition voltage Full-scale transition voltage Symbol -- -- -- -- VOT VFST Pin name -- -- -- -- AN0 to AN31 AN0 to AN31 Value Min -- -- -- -- AVSS - 1.5LSB AVRH - 3.5LSB 1.1 Sampling time tSMP -- 1.65 1.1 Compare time tCMP -- 2.2 2.2 A/D conversion time tCNV -- 3.85 Analog port input current Analog input voltage Standard voltage Power supply current IAH Standard voltage supply current Variation between channels IR AVRH IRH -- AN0 to AN31 -- -- -- -- 5 4 A LSB IAIN VAIN AVRH IA AVCC -- -- -- 600 5 900 A A *4 VAVRH = 5.0 V *4 AN0 to AN31 AN0 to AN31 AVRH -- 0 4.0 -- -- -- -- 2.4 10 AVRH AVCC 4.7 s A V V mA -- -- s s -- -- s s Typ -- -- -- -- AVSS + 0.5LSB AVRH - 1.5LSB -- Max 10 3.0 2.5 1.9 AVSS + 2.5LSB AVRH + 0.5LSB -- Unit bit LSB LSB LSB V V s Remarks 1LSB = (AVRH-AVSS)/1024 VCC = AVCC = 4.5 V to 5.5 V*1 VCC = AVCC = 3.5 V to 4.5 V*5 VCC = AVCC = 4.5 V to 5.5 V*2 VCC = AVCC = 3.5 V to 4.5 V*6 VCC = AVCC = 4.5 V to 5.5 V*3 VCC = AVCC = 3.5 V to 4.5 V*7 VAVSS VAIN VAVCC *1 : When FCP is 40 MHz : tSMP = (Rext + Rin) x Cin x 7 = ST x CLKP cycle = 2 Ah x 25 ns = 1.1 s *2 : When FCP is 40 MHz : tCMP = CKIN x 11 = CT x CLKP cycle x 11 = 4 h x 25 ns x 11 = 1.1 s *3 : This represents the conversion time per channel when tSMP and tCMP are selected while FCP is 40 MHz. (Continued) 62 MB91210 Series (Continued) *4: This defines the power supply current when the A/D converter is not in operation and the CPU is stopped (at "VCC = AVCC = AVRH = 5.0 V") *5 : When FCP is 20 MHz : tSMP = (Rext + Rin) x Cin x 7 = ST x CLKP cycle = 21h x 50 ns = 1.65 s. *6 : When FCP is 20 MHz : tCMP = CKIN x 11 = CT x CLKP cycle x 11 = 4 h x 50 ns x 11 = 2.2 s. *7 : This represents the conversion time per channel when tSMP and tCMP are selected while FCP is 20 MHz. Notes: * As AVRH becomes smaller, the error becomes greater. * Use the output impedance rS of the external circuit for analog input under the following conditions : Output impedance rS of the external circuit = 4 k (Max) * If the output impedance of the external circuit is too high, the sampling time of the analog voltage may not be sufficient. * When placing a DC blocking capacitor between the external circuit and input pin, set the capacitance to the value calculated by multiplying CSH by several thousands as a guideline in order to minimize the impact from dividing voltage capacitance with CSH. * Analog Input Equivalent Circuit Circuit in microcontroller CSH RSH rS Input pin AN0 Comparator Input pin AN7 VS S/H circuit Analog channel selector 63 MB91210 Series TERM DEFINITIONS Resolution Level of analog variation that can be distinguished by the A/D converter. When the number of bits is 10, the analog voltage can be resolved into 210 = 1024. Total error Difference between actual and theoretical values, which is a total value derived from an offset error, gain error, non-linearity error and noise. Linearity error Deviation between the value along a straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") of a device and the full-scale transition point ("11 1111 1110" "11 1111 1111") compared with the actual conversion values obtained. Differential linearity error Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value. * 10-bit A/D Converter- Conversion Characteristics 11 1111 1111 11 1111 1110 11 1111 1101 11 1111 1100 1LSB x N + V0T 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 V0T VNT V (N+1)T VFST N = A/D converter digital output value. V0T = AVss + 0.5LSB [V] (Theoretical value) VFST = AVRH 1.5LSB [V] (Theoretical value) VNT: Transition voltage of digital output from N-1 to N Linearity error= VNT - (1LSB x N + VOT) 1LSB V(N + 1)T - VNT 1LSB [LSB] Differential linearity error= 64 - 1 [LSB] MB91210 Series ORDERING INFORMATION Part No. MB91F211PMC-GSE1 MB91213PMC-GSE1 MB91F213PMC-GSE1 MB91V210PB-ESE1 Package 100-pin plastic LQFP (FPT-100P-M20) 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) 420-pin plastic PBGA (BGA-420P-M01) 65 MB91210 Series PACKAGE DIMENSION 100-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.50 mm 14.0 mm x 14.0 mm Gullwing Plastic mold 1.70 mm Max 0.65 g P-LFQFP100-14x14-0.50 (FPT-100P-M20) Code (Reference) 100-pin plastic LQFP (FPT-100P-M20) 16.000.20(.630.008)SQ Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. * 14.000.10(.551.004)SQ 75 51 76 50 0.08(.003) Details of "A" part INDEX 1.50 -0.10 .059 -.004 (Mounting height) 26 +0.20 +.008 100 0.100.10 (.004.004) (Stand off) 0.25(.010) 0~8 "A" (0.50(.020)) 0.600.15 (.024.006) 1 25 0.50(.020) 0.200.05 (.008.002) 0.08(.003) M 0.1450.055 (.0057.0022) C 2005 FUJITSU LIMITED F100031S-c-2-1 Dimensions in mm (inches). Note: The values in parentheses are reference values Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.htmll (Continued) 66 MB91210 Series (Continued) 144-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Weight 0.50 mm 20.0 x 20.0 mm Gullwing Plastic mold 1.70 mm MAX 1.20g P-LFQFP144-20x20-0.50 (FPT-144P-M08) Code (Reference) 144-pin plastic LQFP (FPT-144P-M08) 22.000.20(.866.008)SQ * 20.000.10(.787.004)SQ 108 73 Note 1) *:Values do not include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 0.1450.055 (.006.002) 109 72 0.08(.003) Details of "A" part 1.50 -0.10 +0.20 +.008 .059 -.004 (Mounting height) INDEX 0~8 0.100.10 (.004.004) (Stand off) 144 37 "A" LEAD No. 1 36 0.50(.020) 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) 0.220.05 (.009.002) 0.08(.003) M C 2003 FUJITSU LIMITED F144019S-c-4-6 Dimensions in mm (inches). Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html 67 MB91210 Series The information for microcontroller supports is shown in the following homepage. http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited Business Promotion Dept. F0702 |
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